Schematic Review 1 Updates

ADXL375 runs at Bus speeds. Higher bus speed → higher data rate
Maybe getting jimfluenced into using a +/- 32 g accelerometer so we have the same high g low g acc. After boost happens, drop range to +/- 4g for higher precision https://www.st.com/en/mems-and-sensors/lsm6dso32.html
Need bisexual ESD protection - was screwing with rs485 + ethernet
Update buzzer schematic. (Choose a passive buzzer, P chanel switching or charge pump with n channel to make sure it actually switches)
Grim pins float on flashing/bootup? might explode the rocket
- and gate with delayed power? i think thats what jim said
- check for FUSA AEQ rating for functional safety: pins dont go high until you tell them
Bens Deployment schematic works but we got lost in the sauce and lost it in altium

Updates since presentation

Using stm32f7 - easier to integrate + still has all the features we need
QSPI flash to mitigate data storage rate worries from grim
STLink MINIE instead of STLink MODS. Less space taken up on board technically less features but covers the features we were planning to use on mods. Maintains compatibility with j-links as theres stdc14 to jtag connectors.
Selected LAN8742A for PHY transceiver. Used on the nucleo for the f7 and we’re going to steal their circuit1
Move BME280, LSM6DSL, ADXL375 to SPI (they all have zephyr drivers and have proven to lock up our i2c bus). MS5611 and INA260 stay on i2c bc we either sample them very slowly or don’t wanna write a SPI driver for MS5611.

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