Secondary Components in Altium:

100nF Ceramic Capacitor: C14663 - In Altium named CC0603KRX7R9BB104
4.7 kΩ Resistor: C23162 - In Altium mhd 12/27/2022 named C23162
10 µF Tantalum capacitor: C7171- In Altium mhd 12/23/2022 named C7171 need to fix footprint
10 nF Ceramic Capacitor: C15195 - In Altium mhd 12/23/2022 named C15195
10 μF Ceramic Capacitor: C13585 - In Altium mhd 12/23/2022 named C13585 - not used anymore
4.7 μF Ceramic Capacitor: C1779 - In Altium mhd 12/23/2022 named C1779
1 μF Capacitor: C52923 - In Altium lff 1/1/2023 named CL05A105KA5NQNC
22 μF Ceramic Capacitor: C12891- In Altium mhd 12/31/22 named C12891
2.2 μH Inductor: C1043 - In Altium 1/19/2023 named CMI201209U2R2KT
10uF Ceramic Capacitor: C1713 - In Altium 1/14/2023 named CL21A106KOQNNNE
600Ω@100MHz Ferrite Bead: C1017 - In Altium 1/22/2023 named GZ2012D601TF
12.4 KΩ Resistor: C22865 - In Altium 1/22/2023 named 0603WAF1242T5E
4.7 µF Ceramic Capacitor: C19666 - In Altium 1/22/2023 named CL10A475KO8NNNC
C2830243 Fuse poly
C187563 fuse (1.5A)
mosfet: C15127 named: AO3401A

Main Component	Secondary Components	JLC Part #	Additional Design Consideration Notes
LC Filter	22 μF Ceramic Capacitor 2.2 μH Inductor	22 μF Ceramic Capacitor: C12891 2.2 μH Inductor: C1043
Barometric Altimeter MS560702BA03- D0ne \|ewis	10 kΩ pull-up resistors 100 nF Ceramic Capacitor	100nF Ceramic Capacitor: C24497 JIM APPROVED ~~10k pull-up Resistor:~~ ~~C25744~~ Not Used	CSB controls last bit of I2C address, should be connected to VDD or GND PS should be tied to VDD for I2C mode 100nF Ceramic Capacitor should be placed as close as possible to VDD
Barometric Altimeter BMP390 - D0ne M-dawg	100 nF capacitor for C1 and C2 4.7 kΩ resistor for R1 and R2	100 nF Capacitor: C24497 - JIM APPROVED 4.7 kΩ Resistor: C23162 - JIM APPROVED	When CSB is connected to VDDIO then I2C interface is active SDO works as I2C Address Pin Select
High G accel ADXL375- D0ne \|ewis	SCL and SDA each need a 10 kΩ pull-up resistor 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor (CS) at VS 0.1 µF ceramic capacitor (CI/O) at VDD I/O	10k pull-up Resistor: C25744 10 µF tantalum capacitor: C7171 - JIM APPROVED 0.1 µF ceramic capacitor: C24497 Louis Fleisher (RIT Student) Mary Dertinger (RIT Student) wut	CS pin tied to VDD I/O ALT ADDRESS pin tied to VDD I/O or GND (determines address) Capacitors should be placed close to the ADXL375 supply pins are recommended to adequately decouple the accelerometer from noise on the power supply. If additional decoupling is necessary, a resistor or ferrite bead (no larger than 100 Ω) in series with VS may be helpful. Additionally, increasing the bypass capacitance on VS to a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor may also improve noise performance.
Microcontroller STM32F446RET6			LQFP64 Package Maybe a bunch of stuff, maybe not ????
Status LEDs JIM
Magnetometer LIS3MDL	Pull-up Resistor Shared With Other ICs Capacitor C1 = 100 nF Low-Frequency Electrolytic Capacitor C2 = 1 μF as near as possible to the supply pin High-Frequency Decoupling Ceramic Capacitor C3 = 100 nF	100 nF Capacitor: C24497 JIM APPROVED 1 μF Capacitor: C1848 100 nF High-Frequency Decoupling Ceramic Capacitor: C24497 JIM APPROVED consider using just ceramics	"There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both the lines are high." CS pin set to 1 for SPI idle mode / I2C communication enabled; set to 0 for SPI communication mode SDO/SA1 pin has to be connected to Vdd_IO or GND to set I2C address
Gyroscope - NOT BEING USED ANYMORE L3GD20H - d0ne mdawg	C1 = 10 nF / minimum 1nF value under 12V bias conditions Between Vdd and GND have 100 nF + 10 μF in parallel If vdd and vdd_IO are not connected, then there must be a 100nF between vdd_IO and GND SCL and SDA each need a 10 kΩ pull-up resistor	10 nF Ceramic Capacitor: C15195 JIM APPROVED (Capacitor cannot physically drop down to the minimum 1nF value at any voltage so that is not a worry.) 100 nF Capacitor: C24497 JIM APPRVED 10 μF Ceramic Capacitor: C13585 JIM APPROVED 10k pull-up Resistor: C25744	Power supply decoupling capacitors (100 nF + 10 μF) should be placed as near as possible to the device (common design practice) If Vdd and Vdd_IO are not connected together, 100 nF and 10 μF decoupling capacitors must be placed between Vdd and common ground while 100 nF between Vdd_IO and common ground. Capacitors should be placed as near as possible to the device (common design practice). CS pin set to 1 for SPI idle mode / I2C communication enabled; set to 0 for SPI communication mode SDO/SA0 pin controls LSB of I2C address (connected to VDD for LSB of 1, GND for LSB of 0) DEN - gyroscope data enable, connect to GND if not used Cap should be connected to GND with ceramic capacitor (10nF (±10%), 25 V. 1nF min value has to be guaranteed under 12 V bias condition
Temp TMP117- d0ne mdawg	5 kΩ pull-up resistor on SCL, SDA, and Alert 100 nF bypass capacitor is recommended to be connected between V+ and GND 0.5 kΩ RC filter on the V+ pin	5 kΩ pull-up Resistor can be substituted with 4.7 kΩ Resistor: C23162 100nF Capacitor: C24497 JIM APPRVED Don't need the 5KΩ on Alert because we are regularly recording temp throughout flight	A power-supply bypass capacitor is required, which must be placed as close to the supply and ground pins of the device as possible. A recommended value for this supply bypass capacitor is 100 nF. Applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise. The user can apply an RC filter to the V+ pin of the device to further reduce noise that the TMP117 might propagate to other components. On V+ Resistor must be 0.5 kΩ or less and capacitor must be 100nF or greater. The TMP117 requires a pullup resistor on the SDA, and ALERT pins. The recommended value for the pullup resistors is 5 kΩ. In some applications, the pullup resistor can be lower or higher than 5 kΩ. A 0.1-μF bypass capacitor is recommended to be connected between V+ and GND. An SCL pullup resistor is required if the system microprocessor SCL pin is open-drain. Use a ceramic capacitor type with a temperature rating that matches thee operating range of the application, and place the capacitor as close as possible to the V+ pin of the TMP117. The ADD0 pin can be connected directly to GND, V+, SDA and SCL for address selection of four possible unique slave ID addresses. The ALERT output pin can be connected to a microcontroller interrupt that triggers an event that occurred when the temperature limit exceeds the programmable value in registers 02h and 03h. The ALERT pin can be left floating or connected to ground when not in use.
Low G Accelerometer MMA8451- D0ne \|ewis	100 nF Ceramic Capacitor on BYP pin 100 nF Ceramic Capacitor on VDDIO pin 4.7 μF Ceramic Capacitor on VDD pin 4.7 kΩ pull-up resistor on SDA and SCL lines	100nF Ceramic Capacitor: C24497 JIM APPRVED 4.7 μF Ceramic Capacitor: C1779 JIM APPROVED 4.7 kΩ pull-up Ceramic Resistor: C23162 - JIM APPROVED	The device power is supplied through VDD line. Power supply decoupling capacitors (100 nF ceramic plus 4.7 μF bulk, or a single 4.7 μF ceramic) should be placed as near as possible to the pins 1 and 14 of the device. The control signals SCL, SDA, and SA0 are not tolerant of voltages more than VDDIO + 0.3 V. If VDDIO is removed, the control signals SCL, SDA, and SA0 will clamp any logic signals with their internal ESD protection diodes.
F\|ash W25Q128JVSIQ - D0ne \|ewis	0.1 μF Decoupling Capacitor?

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