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• 10 kΩ pull-up resistors
• 100 nF Ceramic Capacitor

• CSB controls last bit of I2C address, should be connected to VDD or GND
• PS should be tied to VDD for I2C mode
• 100nF Ceramic Capacitor should be placed as close as possible to VDD

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• When CSB is connected to VDDIO then I2C interface is active
• SDO works as I2C Address Pin Select 

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• CS pin tied to VDD I/O
• ALT ADDRESS pin tied to VDD I/O or GND (determines address)

• Capacitors should be placed close to the ADXL375 supply pins are recommended to adequately decouple the accelerometer from noise on the power supply. If additional decoupling is necessary, a resistor or ferrite bead (no larger than 100 Ω) in series with VS may be helpful. Additionally, increasing the bypass capacitance on VS to a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor may also improve noise performance.

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• "There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both the lines are high."

• CS pin set to 1 for SPI idle mode / I2C communication enabled; set to 0 for SPI communication mode

• SDO/SA1 pin has to be connected to Vdd_IO or GND to set I2C address Image Added

• Power supply decoupling capacitors (100 nF + 10 μF) should be placed as near as possible to the device (common design practice)

• If Vdd and Vdd_IO are not connected together, 100 nF and 10 μF decoupling capacitors must be placed between Vdd and common ground while 100 nF between Vdd_IO and common ground. Capacitors should be placed as near as possible to the device (common design practice).

• CS pin set to 1 for SPI idle mode / I2C communication enabled; set to 0 for SPI communication mode
• SDO/SA0 pin controls LSB of I2C address (connected to VDD for LSB of 1, GND for LSB of 0) 
• DEN - gyroscope data enable, connect to GND if not used
• Cap should be connected to GND with ceramic capacitor (10nF (±10%), 25 V. 1nF min value has to be guaranteed under 12 V bias condition

• A power-supply bypass capacitor is required, which must be placed as close to the supply and ground pins of the device as possible. A recommended value for this supply bypass capacitor is 100 nF. Applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.

• On V+ Resistor must be 0.5 kΩ or less and capacitor must be 100nF or greater. 

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