...
- All connectors are correctly oriented
- Trace pinout of each connector from end to end
- All connectors have silkscreen denoting which pins are which if applicable
- All components have reference designators on silkscreen if possible
- DNP components are not associated with a part number
- All components are updated to their latest revisions
- Schematic is validated and returns no errors or meaningful warnings
- DRC returns ZERO errors and warnings
- Certain errors and warnings may be waived with a valid reason
- Acute angles are minimized
- Layers are properly named
- For 4 layer boards: the JLCPCB 4 layer stackup is used
- Impedance Controlled Traces:
- Traces have the correct impedance using JLCPCB impedance calculator (or whatever fab you are using)
- Traces have transfer vias wherever a layer transition is made
- Traces maintain a constant ground reference plane
- All connections are teardropped when possible
“It shouldn’t have changed from last time” is NOT A CHECK!!!