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Version 3
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Date
Attendees
Goals
- Get updates
- Get comprehensive TODOs between now and JLC delievery
Discussion items
| Item | Who | Notes |
|---|
| Board updates |
|
|
| Software | | Updates:
TODO: - Test W25Q
- Test SHTC3 -
- Test
- Test
- Test
- Test
- Test
- Test
- Test
|
| Radio Module | | Updates: - Added ESD to connectors
- Added UART jumpers to GPS and a debug bus
- Schematic updates "beautified"
- Board Ready for review
To-Do: |
| Power Module |
| Updates: - Design voltage/current sense
- Select passives for most ICs
- Schematic is 60% complete
To-Do: - James May (RIT Student) Update Block Diagram to reflect current design
- James May (RIT Student) simulate umbilical switch in LTspice, look at power loss
- James May (RIT Student) Assemble BOM & include all components
- Create BOM file
- Add switcher
- Add switcher passives
- Add umbilical switch components
- Add monitoring components
- Add monitoring passives
- Add microcontroller
- Add microcontroller passives
- Add WIZnet
- Add WIZnet passives
- Add flash memory
- Add flash passives
- James May (RIT Student) Spec shielded inductors
- James May (RIT Student) Complete schematic capture
- Complete switcher design
- 5V switcher
- 3.3V switcher
- Backplane connector
- current measure
- voltage measure
- WIZnet
- Complete battery/umbilical switch design
- Battery/umbilical switch
- Programming interface
- Add microcontroller & logging circuitry (should be roughly identical to other modules)
- James May (RIT Student) Complete layout
- Place components
- Calculate power trace widths
- Route power traces
- Route signal traces
- James May (RIT Student) Simulate switchers in Webench
|
| Sensor Module |
| Updates:
TODOs: |
Action items