Secondary Components

• 10 kΩ pull-up resistors
• 100 nF Ceramic Capacitor

• CSB controls last bit of I2C address, should be connected to VDD or GND
• PS should be tied to VDD for I2C mode
• 100nF Ceramic Capacitor should be placed as close as possible to VDD

• When CSB is connected to VDDIO then I2C interface is active
• SDO works as I2C Address Pin Select 

10k pull-up Resistor: C25744 

10 µF tantalum capacitor: C7171 - JIM APPROVED

0.1 µF ceramic capacitor: C24497 Louis Fleisher (RIT Student) Mary Dertinger (RIT Student) wut 

• CS pin tied to VDD I/O
• ALT ADDRESS pin tied to VDD I/O or GND (determines address)

• Capacitors should be placed close to the ADXL375 supply pins are recommended to adequately decouple the accelerometer from noise on the power supply. If additional decoupling is necessary, a resistor or ferrite bead (no larger than 100 Ω) in series with VS may be helpful. Additionally, increasing the bypass capacitance on VS to a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor may also improve noise performance.

  
  

• "There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both the lines are high."

• CS pin set to 1 for SPI idle mode / I2C communication enabled; set to 0 for SPI communication mode

• SDO/SA1 pin has to be connected to Vdd_IO or GND to set I2C address

• Power supply decoupling capacitors (100 nF + 10 μF) should be placed as near as possible to the device (common design practice)

• If Vdd and Vdd_IO are not connected together, 100 nF and 10 μF decoupling capacitors must be placed between Vdd and common ground while 100 nF between Vdd_IO and common ground. Capacitors should be placed as near as possible to the device (common design practice).

• CS pin set to 1 for SPI idle mode / I2C communication enabled; set to 0 for SPI communication mode
• SDO/SA0 pin controls LSB of I2C address (connected to VDD for LSB of 1, GND for LSB of 0) 
• DEN - gyroscope data enable, connect to GND if not used
• Cap should be connected to GND with ceramic capacitor (10nF (±10%), 25 V. 1nF min value has to be guaranteed under 12 V bias condition

• A power-supply bypass capacitor is required, which must be placed as close to the supply and ground pins of the device as possible. A recommended value for this supply bypass capacitor is 100 nF. Applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.

• The user can apply an RC filter to the V+ pin of the device to further reduce noise that the TMP117 might propagate to other components. 

• On V+ Resistor must be 0.5 kΩ or less and capacitor must be 100nF or greater. 

• The TMP117 requires a pullup resistor on the SDA, and ALERT pins. The recommended value for the pullup resistors is 5 kΩ. In some applications, the pullup resistor can be lower or higher than 5 kΩ. A 0.1-μF bypass capacitor is recommended to be connected between V+ and GND. An SCL pullup resistor is required if the system microprocessor SCL pin is open-drain. Use a ceramic capacitor type with a temperature rating that matches thee operating range of the application, and place the capacitor as close as possible to the V+ pin of the TMP117. The ADD0 pin can be connected directly to GND, V+, SDA and SCL for address selection of four possible unique slave ID addresses. 

• The ALERT output pin can be connected to a microcontroller interrupt that triggers an event that occurred when the temperature limit exceeds the programmable value in registers 02h and 03h. The ALERT pin can be left floating or connected to ground when not in use.

• The device power is supplied through VDD line. Power supply decoupling capacitors (100 nF ceramic plus 4.7 μF bulk, or a single 4.7 μF ceramic) should be placed as near as possible to the pins 1 and 14 of the device.

• The control signals SCL, SDA, and SA0 are not tolerant of voltages more than VDDIO + 0.3 V. If VDDIO is removed, the control signals SCL, SDA, and SA0 will clamp any logic signals with their internal ESD protection diodes.