SPICA Design Verification
- Joseph Even (RIT Student)
Owned by Joseph Even (RIT Student)
Sept 26, 2020
1 min read
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| System | Procedure | Check |
|---|---|---|
| Power Supply | Y | |
| uC Reset | Y | |
| Deployment Channel | Y | |
| Deployment Continuity | Y |
| System | Procedure | Check |
|---|---|---|
| Power Supply | Y | |
| uC Reset | Y | |
| Deployment Channel | Y | |
| Deployment Continuity | Y |